Mohammad Ewais
PhD in Computer Engineering | ML/HPC Architect
I'm currently doing my PhD in Computer Engineering at the University of Toronto, I also work as a ML/HPC Architect at AMD. I have earned my MASc degree from the University of British Columbia, and before that I finished my BSc from Alexandria University. In my PhD, I am currently focused on exploring disaggregated memory architecture for datacenter. At AMD, I work on designing/architecting a line of datacenter GPUs to better support machine learning applications. I possess a strong passion for computer architecture, digital design, and CAD tools. With a comprehensive background spanning hardware and software, I have accumulated over 3 years of experience in ASIC/FPGA design, conducted research in computer architecture and memory hierarchy optimizations for 5+ years in both academia and industry, and contributed to LLVM-based compiler development for over 1 year.
Professional Experience
ML/HPC Architect
Design and architect datacenter GPUs for machine learning applications. Perform workload analysis, theoretical analysis, and ROI calculations for new architecture features.
Compilers Engineer
Worked on LLVM-based compiler for in-house GPU. Responsible for TableGen pattern matching, optimization passes, and C model debugging.
Teaching Assistant
Taught digital systems design and microprocessors courses.
Research and Teaching Assistant
Research on STT-RAM as main memory and taught various computer engineering courses.
Education
Academic journey through computer engineering and research
PhD in Computer Engineering
Focus on disaggregated memory architecture for datacenter applications
MASc in Computer Engineering
Specialized in cache compression and computer architecture
BSc in Communications and Electronics
Foundation in electrical engineering and digital systems
Skills & Expertise
A comprehensive overview of my technical skills and expertise across various domains
Programming
Concepts
Languages
Skills Overview
Programming
Digital Design
Computer Architecture
Machine Learning
Cloud
Miscellaneous
Publications
Research contributions in computer architecture, memory systems, and FPGA acceleration
2023
Disaggregated Memory in the Datacenter: A Survey
Mohammad Ewais, Paul Chow
IEEE Access 11 (2023)
2022
The Future of FPGA Acceleration in Datacenters and the Cloud
Bobda, Christophe, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 15.3 (2022)
2021
A Framework Integrating FPGAs in VNF Networks
Mohammad Ewais, Juan Camilo Vega, Alberto Leon-Garcia, Paul Chow
2021 12th International Conference on Network of the Future (NoF)
FFIVE: An FPGA Framework for Interactive VNF Environments
Juan Camilo Vega, Mohammad Ewais, Alberto Leon-Garcia, Paul Chow
2021 IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM 2021)
2020
Decoupling Approximation and Cache Compression
Amin Ghasemazar, Mohammad Ewais, Mieszko Lis
2020 Workshop on Approximate Computing Across the Stack (WAX 2020)
2DCC: Cache Compression in Two Dimensions
Amin Ghasemazar, Mohammad Ewais, Prashant Nair, Mieszko Lis
2020 Design, Automation and Test in Europe Conference and Exhibition (DATE 2020)
2018
2016
2014
Smart employment of circuit redundancy to effectively counter trojans (SECRET) in third-party IP cores
Mohammed M Farag, Mohammad A Ewais
2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)
Research Impact
My research spans computer architecture, memory systems, cache compression, FPGA acceleration, and datacenter disaggregation. I focus on practical solutions that bridge the gap between theoretical research and real-world applications in high-performance computing.
Let's Connect
Interested in collaboration, research opportunities, or just want to chat about computer architecture?
Contact Information
Location
Toronto, Canada